1. Field of the Invention
The present invention relates in general to the prevention of a heartbeat collision, and more particularly to heartbeat collision prevention circuit and method in which accesses of computer stations to a data line are controlled in a data communication system in which the computer stations are networked, so that the computer stations can be fair in the data transmission order.
2. Description of the Prior Art
Generally, in a system, such as a local area network (LAN), in which many computers or workstations are interconnected to one another to share and exchange data among them it is most important to control efficiently the stations so that two or more of the stations cannot gain simultaneous accesses to a data line. To this end, there has been proposed a carrier sense multiple access (referred to hereinafter as CSMA) manner in which the first station occupying the data line acquires a priority, so as to transmit the data before others. However, in the CSMA manner, when two or more of the stations determine that the data line is not occupied by other stations and then transmit the data simultaneously, a data collision occurs, resulting in a degradation in a communication efficiency. In order to prevent such a data collision, a heartbeat collision prevention circuit is employed in each of adapter circuits connected respectively to the stations.
Referring to FIG. 1, there is shown an example of data communication networks employing the CSMA manner. As shown in this drawing, four individual stations 1-4 are connected in parallel to data and heartbeat signal lines through adapter circuits 6, respectively. Dip switches 5 are connected to the adapter circuits 6, respectively. Inherent addresses are assigned to the stations 1-4, respectively. A slot time indicating a data transmission time point is assigned to each of the stations 1-4 according to the assigned address and a heartbeat signal, so that each of the stations 1-4 can transmit the data for its slot time. The dip switches 5 are adapted to assign the addresses to the corresponding stations 1-4, respectively.
Referring to FIG. 2, there is shown a block diagram of a conventional heartbeat collision prevention circuit 20 which is disposed in each of the adapter circuits 6 in FIG. 1. As shown in this drawing, the conventional heartbeat collision prevention circuit 20 comprises an edge detector 21 for detecting an edge of an input heartbeat signal, a 12-bit counter 22 for inputting an output signal from the edge detector 21 as its load signal and a signal of 895 KHz as its clock signal and counting input data D0-D11 in response to the inputted signals, and a 4-bit counter 23 for inputting a carrier detect signal as its load signal and a signal of 112 KHz as its clock signal and counting input data D0-D3 in response to the inputted signals. The carrier detect signal indicates that a different station is now in data transmission.
The conventional heartbeat collision prevention circuit 20 also comprises a D flip-flop 24 for inputting an output signal Q11 from the 12-bit counter 22 as its clock signal, latching its inverted output signal /Q in response to the inputted signal and outputting the latched signal as a heartbeat signal, a D flip-flop 25 for inputting the output signal Q11 from the 12-bit counter 22 as its clock signal, latching an output signal from an AND gate AN1 in response to the inputted signal and outputting the latched signal as a transmit enable signal, an inverter IN1 for inverting a master select signal MSLT, a NAND gate NA1 for NANDing an output signal from the inverter IN1 and the output signal Q11 from the 12-bit counter 22 and outputting the resultant signal as an enable signal to the 12-bit counter 22, and an inverter IN2 for inverting an output signal Q3 from the 4-bit counter 23 and outputting the inverted signal as an enable signal to the 4-bit counter 23. The AND gate AN1 is adapted to AND the output signal Q3 from the 4-bit counter 23 and a service request signal and output the resultant signal to the D flip-flop 25.
The operation of the conventional heartbeat collision prevention circuit 20 with the above-mentioned construction will hereinafter be described.
When the heartbeat signal is generated from a master station, for example the station 4, for the data transmission and reception, it is applied to the edge detector 21 in the heartbeat collision prevention circuit 20 which is disposed in the adapter circuit 6 connected to each station. At this time, whenever the input heartbeat signal goes from "0" to "1" and vice-versa in logic, the edge detector 21 outputs a high logic signal as the load signal to the 12-bit counter 22. The 12-bit counter 22, when its clock signal goes form "0" to "1" in logic, performs the following operation. When the load signal from the edge detector 21 is "1" in logic, the 12-bit counter 22 loads the input data D0-D11. In the case where the load signal from the edge detector 21 is "0" in logic and the enable signal from the NAND gate NA1 is "1" in logic, the 12-bit counter 22 increments its count. If both the load signal from the edge detector 21 and the enable signal from the NAND gate NA1 are "0" in logic, the 12-bit counter 22 has no variation in the operation. Similarly, the 4-bit counter 23 is operated in the same manner as that of the 12-bit counter 22.
The 4-bit counter 23 acts as a time-out circuit which, for a predetermined time period after the transmission of the last data is completed, delays the transmission of the subsequent data to prevent the data collision. The output signal Q3 from the 4-bit counter 23 becomes "1" in logic when the data line of the network is free. On the other hand, whenever the carrier detect signal indicating that a different station is now in data transmission is made active, logic "0" is loaded into the 4-bit counter 23 and the output signal Q3 of the 4-bit counter 23 is thus set to "0" in logic to indicate that the data line is not free. If the carrier detect signal is made inactive, the 4-bit counter 23 starts the counting operation. The output signal Q3 from the 4-bit counter 23 goes "1" in logic when the count thereof becomes "8". The logic "1" output signal from the 4-bit counter 23 indicates that the data transmission is enabled because of the lapse of an interframe spacing time. Here, the interframe spacing time signifies a desired minimum time interval between frames in the data transmission in the unit of frame. If the output signal Q3 from the 4-bit counter 23 becomes "1" in logic at the moment that the interframe spacing time is ended, the enable signal from the inverter IN2 goes "0" in logic. As a result, no further increase is present in the count of the 4-bit counter 23 after the lapse of the interframe spacing time.
The 12-bit counter 22 is operated in response to the input heartbeat signal to assign the slot time to the corresponding station. Namely, when the output signal Q11 from the 12-counter 22 goes from "0" to "1" in logic, the slot time is assigned to the corresponding station. Whenever the input heartbeat signal is changed in logic, the output signal from the edge detector 21 goes "1" in logic, thereby causing the 12-bit counter 22 to load the input data D0-D11. Here, bits D5-D10 of the input data D0-D11 are a binary complement of the corresponding station address and a most significant bit D11 thereof is "0" so that an initial state of the output signal Q11 from the 12-bit counter 22 can become "0" in logic. Then, when the load of the input data D0-D11 is completed, the 12-bit counter 22 starts the counting operation. In this case, the number of counting times for a logic "0" to "1" transition of the output signal Q11 from the 12-bit counter 22 is 32 times the station address.
The operation of the 12-bit counter 22 after its output signal Q11 becomes "1" in logic is performed depending on whether the corresponding station is a master. If the corresponding station is not the master, the master select signal MSLT becomes "0" in logic. The NAND gate NA1 outputs a low logic signal as the enable signal to the 12-bit counter 22 because both the input signals are "1" in logic. As a result, the 12-bit counter 22 stops the counting operation.
On the other hand, if the corresponding station is the master, the master select signal MSLT becomes "1" in logic, thereby causing the NAND gate NA1 to output a high logic signal as the enable signal to the 12-bit counter 22. As a result, the 12-bit counter 22 continues to perform the counting operation even after the time-out. Namely, the 12-bit counter 22 generates the heartbeat signal continuously even when it can receive no heartbeat signal because of the time-out.
The D flip-flops 25 and 24 are adapted to generate the transmit enable signal and the heartbeat signal, respectively. The D flip-flop 25 is operated when the output signal Q11 from the 12-bit counter 22 is changed from "0" to "1" in logic, namely, the slot time is assigned to the corresponding station. At this time, if the service request signal from a control logic (not shown) is made active to indicate that the corresponding station is ready to transmit the data and the output signal Q3 from the 4-bit counter 23 becomes "1" in logic to indicate that the data line of the network is free, the output signal or the transmit enable signal from the D flip-flop 25 becomes "1" in logic. If the above two conditions are not satisfied, the transmit enable signal from the D flip-flop 25 remains at its logic "0" state unit the next slot time occurs. The transmit enable signal from the D flip-flop 25 is fed back to a preset terminal of the D flip-flop 25, so that it can remain at its logic "1" state regardless of the input signal D once being become "1" in logic. When the data transmission of the corresponding station is completed, a transmit complete signal from the control logic is applied to a clear terminal of the D flip-flop 25 to clear the D flip-flop 25. As a result, the transmit enable signal from the D flip-flop 25 returns to its logic "0" state. If the data transmission is completed as mentioned above, the data line of the network becomes free and each station gains access to the data line for its slot time after the lapse of the predetermined interframe spacing time.
On the other hand, in the case where a priority is assigned to a specified station, the D flip-flop 24 outputs the heartbeat signal if the specified station is the master. Then, when the output signal Q11 from the 12-bit counter 22 is changed from "0" to "1" in logic, the output signal Q from the D flip-flop 24 is changed from "0" to "1" and vice-versa in logic. In result, the heartbeat signal from the D flip-flop 24 makes a transition at the same time that the slot time is assigned to the master station. In the case where the specified station is not the master, the D flip-flop 24 is not operated.
FIGS. 3A to 3F are timing diagrams illustrating an example in which the slot times are assigned to the stations 1-4 in FIG. 1 in consideration of the heartbeat signal and the interframe spacing time, the heartbeat signal being generated from the master station 4. From these drawings, it can be seen that the heartbeat signal makes a transition at the same time that the slot time is assigned to the master station. Also, the stations 1-3 are timed out earlier than the master station. This reason is that the time-out is determined according to the predetermined time interval and the station addresses. Because the highest-order station address is assigned to the master station, other stations must be all timed out before the heartbeat signal from the master station makes a further transition.
In detail, when the heartbeat signal from the master station makes a first transition, the counters in the adapter circuits 6 of the stations 1-4 are initialized to perform the counting operations. Then, each station is timed out for a time-out interval based on the corresponding station address. In FIGS. 3A to 3F, a falling edge of each of time-out pulses in each station designates the transmission slot time ST of the corresponding station. For example, in the station 2, the first slot time occurs at a moment t2, at which the D flip-flop 25 generates the transmit enable signal upon receiving the service request signal from the control logic and the output signal from the 4-bit counter 23 indicating that the interframe spacing time has been satisfied. As shown in FIG. 3F, an end-of-data transmit signal EDT is generated between a moment t1 and the moment t2 and the interframe spacing time IFS is ended between the moment t2 and a moment t3. As a result, since the interframe spacing time or the second condition for generating the transmit enable signal at the first slot time in the station 2 is not satisfied, the station 2 cannot transmit the data till a moment t6 that the next slot time occurs.
In the station 3, the first slot time occurs at the moment t3. The station 3 can transmit the data at the moment t3 upon receiving the service request signal from the control logic, because the moment t3 is beyond the range of the interframe spacing time IFS. Provided that the station 3 has no data to transmit, the service request signal from the control logic becomes "0" in logic and the station 3 waits till a moment t7 that the next slot time occurs.
However, the above-mentioned conventional heartbeat collision prevention circuit has a disadvantage in that the priority is assigned to only the specified station because the transmission order is fixed due to the slot time fixed every station. Namely, the stations cannot gain fair accesses to a channel. Also, in the case where many stations are connected to the network, the heartbeat signal from the master station has a long duration. The long duration of the heartbeat signal cause the time interval between the data transmissions to become long, resulting in a degradation in a performance of the entire network.